The present invention generally relates to integrated circuit (IC) structures in complementary metal oxide semiconductor (CMOS) circuits and, more particularly, to a new method for integrating an embedded high capacitance, low leakage decoupling capacitor on silicon on insulator (SOI) or bulk wafers for very high performance CMOS microprocessors.
The goal for semiconductor designers is to design highly reliable, super high performance CMOS microprocessors with ever increasing functionality requirements, while consuming the lowest possible power. This becomes more important for low power battery operated devices where battery operating lifetime is crucial.
In this mode of operation, circuit designers face a number of challenges to insure high signal integrity within the chip and the semiconductor package. Simultaneous switching through the input and output (I/O) pins give to current xe2x80x9cnoisexe2x80x9d spike xcex4I within a specified time, severely degrading the signal integrity. The signal integrity is jeopardized mainly by the xe2x80x9cnoisexe2x80x9d on the power and ground planes due to the capacitance coupling between power and signal lines. These noises become more severe as the clock frequency or the I/Q pin count is increased.
To insure the system reliability against such deleterious effects, decoupling capacitors, known as Decap, are added to the power and ground planes to provide an AC ground for the noise and provide a stable DC voltage. The value of the Decap is usually modeled by:
Decoupling Cap (Decap)=Current spike xcex4Ixc3x97Time/(xcex4V Voltage Noise)
Currently, the methodology for embedding a Decap on a microprocessor is to use available structures in the semiconductor process flow; i.e., N-type field effect transistor (NFET), P-type field effect transistor (PFET), or capacitors, all of which strongly depend on the thickness of the gate oxide (Tox) used to meet the necessary capacitance predicted in the above equation. As oxide thickness is scaled down, in order to increase the capacitance value in a preset silicon active area, the gate current leakage will increase accordingly. It has been determined experimentally that the gate leakage current increases by a factor of 2.5-3 times for every 1 Angstrxc3x6m (1 xc3x85) of gate oxide scaling.
In order to increase the gate capacitance and reduce power dissipation and at the risk of increased process complexity and cost, it is possible to build a process with multiple gate oxide offering:
the xe2x80x9cthin gate oxidexe2x80x9d for high performance NFET and PFET devices;
the other xe2x80x9cthick gate oxidexe2x80x9d for the Decap capacitance with limited leakage value to reduce the power dissipation, but reduced capacitance; and
another possible method is to introduce a third xe2x80x9cintermediatexe2x80x9d gate oxide which balances the increased gate capacitance, but at the risk of increased gate leakage.
State of the art microprocessor Decap requires as much as a micro Farad (1 xcexcF) designed in a half centimeter square area (0.5 cm2). A significant amount on a required silicon real estate area in light of the reduced number of chips which can be placed on a wafer and the reduced profit associated with this.
Table 1 describes an example of an available microprocessor surface area which can be used to obtain a Decap requirement of 1 xcexcF, using various thin and thick oxide values. As an example, DG represents the xe2x80x9cthick gate oxidexe2x80x9d of 22 xc3x85, the xe2x80x9cthin gate oxidexe2x80x9d of 10 xc3x85 or a combined area of xe2x80x9cthinxe2x80x9d and xe2x80x9cthickxe2x80x9d and xe2x80x9cintermediatexe2x80x9d gate oxide of 15 xc3x85.
[t1]
FIG. 1 shows the calculated Decap value in micro Farads (xcexcF) as a function of gate oxide thickness in nanometers for an available area of 0.54 cm2 on a typical high performance microprocessor design. Note that for a robust signal integrity design, a Decap capacitance of 1 xcexcF is required, where only 0.6 to 0.8 xcexcF can be provided using the current planar gate oxide decap method and the limited set silicon area.
FIG. 2A shows the current standard method of forming a planar Decap on SOI, starting with a thin gate oxide on silicon wafer which forms the bottom plate of the capacitor. Although the object of the invention is not the Silicon On Insulator (SOI) formation itself, it is described here for clarity of understanding the preferred embodiment of the invention. One method of forming such an SOI substrate wafer is through the implantation of oxygen specie at high energy as to embed the oxygen deep in the silicon substrate 1 and leave a layer of silicon 3 free from oxygen on top of the oxygen level. This is followed by an annealing step at high temperature, which results in the formation of a buried silicon dioxide (BOX) layer 2, below a shallow silicon layer, (layer 3) on top of the BOX layer 2 on the silicon substrate 1.
The silicon layer 3 is divided into regions by shallow trench insulation (STI) 4 and, by process of patterning with photoresist and doping well known in the art, the respective regions are made to be n-type or p-type regions, as shown. The structure is then wet cleaned, and a thick gate oxide 5 is formed. Then a photoresist is spun on, patterned and developed to protect the thick gate oxide. The exposed area is then wet etched to remove the unprotected thick gate oxide. Next, the photoresist is stripped and a thin gate oxide 6 is grown.
FIG. 2B shows a standard method for gate interconnect polysilicon deposition to form the top plate of the capacitor. More specifically, a low pressure chemical vapor deposition (LPCVD) of polysilicon 7 covers the entire structure to a thickness of 150 nm. Then, by plasma enhanced chemical vapor deposition (PECVD), a 50 nm layer of gate capacitor oxide 8 is deposited. An anti-reflective coating (ARC) 9 to a thickness of 90 nm is deposited, followed by a photoresist layer 10 to a thickness of 240 nm. The photoresist layer 10 is patterned, exposed and developed to form the mask in the form of 70 nm wide resist lines.
FIG. 2C shows a planar Decap polysilicon lithographic pattern. Although only single fingers of polysilicon are shown for the sake of clarity, in practice the Decap must be designed with multiple fingers of polysilicon lines for defect reasons. After etching back to the thick and thin gate oxides 5 and 6, the photoresist 10 and the anti-reflective coating 9 are stripped, leaving the polysilicon lines 11.
The left sides of FIGS. 3A and 3B show, respectively, a top view and a side view in schematic representation of the planar Decap structure formed by the process described with respect of FIGS. 2A, 2B and 2C. It will be immediately apparent from FIG. 3A the relatively large active area required by the planar Decap structure.
It is therefore an object of the present invention to provide a new structure and process to form a new Decap Trench Capacitor (DTC) which provides increased capacitance within in a smaller active silicon area than prior planar Decap capacitors.
It is another object of the invention to provide a new semiconductor method of integrating Decap trench capacitors on SOI for the purpose of accomplishing a robust circuit design with low noise while reducing the active silicon area used.
According to one aspect of the invention, there is provided a new semiconductor Decap Trench Capacitor (DTC) integrated on a SOI for the purpose of accomplishing a robust circuit design with low noise while reducing the silicon area used. The DTC for SOI devices comprises a buried oxide layer on a silicon substrate with a silicon layer over the buried oxide layer. Shallow trench insulation extends to the buried oxide layer in the silicon layer. A first trench is formed in the shallow trench insulation and extends through the buried oxide layer into the silicon substrate. The first trench has formed on the walls thereof an oxide insulating layer, serving as the dielectric for the capacitor, and this trench is then filled with polysilicon to form the DTC. A second trench is formed in the silicon layer adjacent to the first trench and extends through the buried oxide layer into the silicon substrate. The second trench is filled with polysilicon and forms the substrate contact for the DTC.
The DTC is manufactured beginning with a first lithography step to form a mask on top of a SOI substrate followed by an etch step to form trenches of various depth through the buried oxide BOX layer to define a capacitor region and a substrate contact region. An implant step inside the substrate contact region can be performed to lower the contact resistance to the substrate. This is followed by a thin oxidation step or deposition step on the surface of the wafer and inside the trench to form the basis for the dielectric for the desired capacitor. A second lithography step is performed to define over the capacitor region and expose the substrate contact region. A wet etch step is used to etch the grown or deposited oxide inside the substrate contact region without etching the oxide inside the capacitor region. A top layer of conductive material (i.e., polysilicon) is deposited to fill the capacitor region and the substrate contact region followed by a chemical mechanical polishing. The polysilicon surface forms the top plate for the capacitor, while simultaneously forming the contact to the substrate bottom plate capacitor.